IEEE

Design and Implementation of D Flip-Flop using T and JK Flip-Flop based on PTL in 90nm Technology

Abstract: This investigation concentrates on the design and analysis of D flip-flops using Pass Transistor Logic (PTL) in 90nm CMOS technology, with implementation carried out in Cadence Virtuoso.
GitHub

JK Flip-Flop Using NAND Gates

This project is a gate-level implementation of a JK flip-flop using only NAND gates, built and simulated in Logisim Evolution (v3.7.2). The idea was to understand how the JK flip-flop works internally ...
IEEE

High Performance Flip-Flop Design Using a New Output Latch Scheme in Samsung 2nm GAA Process

With the continuous evolution of semiconductor technology, System-on-Chip (SoC) designs are becoming increasingly complex, demanding higher performance while meeting tight power and area constraints ...
IEEE

Design and Implementation of a Low-Power 4-Bit Synchronous Up Counter Using Gate-Diffusion Input Technology

Abstract: Power efficiency together with speed and design area optimization represent essential factors which matter significantly for contemporary digital circuit design activities including embedded ...
IEEE

Design of Low Power TG Based FinFET D-Flip Flop for Memory Cell Architecture

Abstract: This article presents innovative research with regard to the design and analysis of a low-power transmission gate-based D-flip-flop circuit with implementation using FinFET technology. The ...
IEEE

Design and Testing of a Direct Oil-Cooled Homopolar Synchronous Generator With Dual DC-Link via Diode Rectifiers

Abstract: The drivetrains of large transportation systems, such as aircraft or ships, are evolving toward hybrid configurations with dc primary power distribution thanks to their higher efficiency. In ...
IEEE

Gain Design Method for Active Damping Control in Mono-Inverter Dual Parallel Permanent Magnet Synchronous Motors Drive Systems

Abstract: This paper proposes a gain optimization method for an active damping controller in a mono-inverter dual parallel permanent magnet synchronous motors drive system. In this system, two motors ...
IEEE

Radiation-Hardened Flip-Flop Design Using Dice and Quatro Cell for Enhanced Soft-Error Resilience

Abstract: This Study Proposes, in order to improve softerror resistance against Single Event Upsets (SEUs) and Double Node Upsets (DNUs), a radiation-hardened flip ...
IEEE

Design and Comprehensive Analysis of Magnetic-Geared Permanent Magnet Synchronous Motor for Single-Propeller Underwater Propulsion

Abstract: This paper presents a magnetic-geared permanent magnet synchronous motor (MG-PMSM), which is an integrated structure composed of a permanent magnet synchronous motor (PMSM) and a magnetic ...
IEEE

Design and Analysis of Double Voltage Self-Powered Synchronous Switch Interface Circuit for High Impedance Piezoelectric Energy Harvesting

Abstract: Although the synchronized switch harvesting on inductor (SSHI) circuit can obtain eight times the energy of the standard energy harvesting (SEH) circuit at its optimal impedance, the energy ...
IEEE

Synchrophasor-Based Parameter Identification of Sub/Super-Synchronous Oscillations Using Adaptive Empirical Fourier Decomposition

Abstract: Synchrophasor-based sub-synchronous oscillation (SSO) parameter identification is effective for monitoring SSOs, while its performance can be significantly affected by measurement noise, ...
IEEE

CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop Using Transmission Gate Logic for Low Power VLSI Applications

Abstract: The rapid evolution of low-power applications in VLSI design calls for innovative transistor technologies that are capable of meeting stringent energy efficiency requirements. Carbon ...