Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Design-Reuse

Imec Teams With Cadence to Present Automated Design-for-Test (DFT) Solution for 3D Memory-on-Logic

LEUVEN, Belgium, 22 Jan 2013-- At the European 3D TSV Summit in Grenoble, France on January 22-23, 2013, imec, a world-leading nano-electronics research institute, today announced that together with ...
EDN

How to generate test patterns to detect FinFET defects

The size and performance advantages of FinFETs are leading to a general industry adoption of these 3D transistors at the more advanced technology nodes. These complex transistors, however, exacerbate ...
Semiconductor Engineering

Power-Aware Revolution In Automated Test For ICs

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and ...
EDN

Cadence and Imec introduce 3D IC Memory on logic DFT

One of the predictions made by many people for 2013, was the growth in adoption of 3D chip technologies. We have already seen it for FPGA assemblies and has been in production use for memories for ...