As processes continue to move to 0.13 micron and below, the challenge of ensuring signal integrity on a chip increases. Crosstalk between signals is the most severe problem that impacts signal timing, ...

FIFO and handshake synchronizers pose special difficulties; new tools are the answer Among the many verification challenges confronting system-on-chip (SOC) designers these days, clock domain ...

Static and dynamic code analysis can improve application performance, safety and reliability by identifying problems early in the development cycle if the proper tools and procedures are used from the ...