Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...
EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Design-Reuse

Tensilica Announces Major IC Design Automation Breakthrough, The Automatic Generation of Optimized Programmable RTL Engines from Standard C Code

SANTA CLARA, Calif. - Sept. 6, 2004 - Tensilica(R), Inc. today announced that it has achieved a major design automation breakthrough - the automated design of optimized configurable processors from ...
EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Design-Reuse

Real-World Reuse: RTL Recycling

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...