Semiconductor Engineering

Are You Using Structural Patterns In An SLT Environment?

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Semiconductor Engineering

Better ATPG To Minimize Chip Test Time And Cost

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
EDN

Decreasing Cost-of-Test with Automatic Test-Pattern Generation

Success in the electronics business hinges on producing high-quality products and using the most cost-effective methods to do so. As the number of devices on ICs continues to double every 18 to 24 ...