Design-Reuse

ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

Companies Also Announce Addition of HDL Works to Actel's EDA Alliance Program CAMBERLEY, UK and EDE, Netherlands, July 26 -- Actel Corporation (Nasdaq: ACTL) and HDL Works today announced the ...
EDN

HDL: A Design Flow Runs Through It

The modern hardware design flow is beginning to resemble America's great rivers. At one time they ran wild and free, but now they are constrained by an endless series of irrigation projects, dams and ...
EDN

HDL tool aids IC design flow

Version 6.0 of EASE design-entry environment for VHDL, Verilog, and mixed-language FPGAs and ASICs provides features for both advanced and novice HDL designers. HTML generation for any HDL design is ...
Electronic Design

Meeting customers’ demand for easing HDL designs

Actel and HDL Works have jointly optimised HDL Works’ EASE design entry tool for Actel’s Libero Integrated Design Environment (IDE) design flow. The EASE Graphical HDL Design Entry environment ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
Electronic Design

Programmable Logic: To HDL Or Not To HDL?

Strategies for EDA tool usage will change course as gate levels, and ultimately costs, rise in programmable logic designs. For designs below 25,000 gates, the basic tools from logic vendors and many ...
ITWire

iTWire - HDL Design House Adopts Magma's Chip Design Software

With Magma as its primary EDA vendor, HDL Design House will now be able to provide its clients with complete mixed-signal system on chip (SoC) design services, and be able to augment their current ...
Semiconductor Engineering

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)

LLM-aided interface for Open Source Chip Design,” was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract “The growing complexity of hardware design and the ...