EDN

Frequency Divider Using T Flip Flop Configuration

The circuit was constructed to produce a frequency divider with the use of flip flops which are the basic building blocks of sequential logic circuits while forming a T flip-flop configuration. Toggle ...
EDN

Frequency divider from 1 to 4096 in increments of 1

Frequency dividers are usually realized on ICs and have a fixed and small division coefficient. In this article, a frequency divider is proposed that allows you to set the frequency division ...
Design-Reuse

Programmable CMOS frequency divider (56..16383 dividing ratio)

The cell is 14-bit programmable frequency divider. It consists of CMOS prescaler with variable dividing ratio 8/9 controlled by 3-bit swallow counter ...
Design-Reuse

Design Tip: Implementing an SoC with dependable 50% duty cycles

With the increased integration and movement towards system-on-chip (SoC) designs, it is becoming increasingly challenging to satisfy the diverse clocking requirements of the ever increasing functions ...
BBC

The Binary counter as a frequency divider for television

This report describes the application of the binary counter circuit to television master timing-pulse generators as an improvement on previous practice. © BBC. All ...