EDN

FPGA transceiver test goes on-chip through Windows

New Analysis Environment for Multi-Gigabit Transceivers in Virtex-4 and Virtex-5 Platforms Delivers Ease-of-Use and Productivity Boost to System Designers The new tool will be used by design teams in ...
Design-Reuse

Xilinx Announces ChipScope Pro 9.1i Software - Extending Serial I/O Debug Capabilities to Support 65nm Virtex-5 LXT FPGAs

New release delivers 60% faster clock speeds and comprehensive low-cost BERT capabilities for RocketIO multi-gigabit transceivers SAN JOSE, Calif. -- Jan. 29, 2007 -- Xilinx, Inc. today announced the ...
EDN

Binding the “Ties that Break” – Getting FPGA and PCB designers to meet at the I/O pin negotiating table

With their zero NRE and shorter design cycles, FPGA's are steadily replacing ASIC's in mid-level commercial and even higher-volume consumer applications. But as FPGA usage has steadily grown, so have ...
Railway Technology

Flexible FPGA and I/O Designs with Kontron’s Extended VITA 57 Offering

Kontron has announced the introduction of two new products, the Kontron FPGA mezzanine card FMC-SER0 and the Kontron VITA 57 development kit KIT-FMC-DEV, rounding off a robust portfolio of VITA 57 ...
Design-Reuse

A Reconfigurable System featuring Dynamically Extensible Embedded Microprocessor, FPGA and Customisable I/O

A system-chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an ...