EDN

Debugging hybrid FPGA logic/processor designs

FPGAs continue to advance, enabling ever more integration of programmable technologies into the heart of embedded systems. Today’s high-performance FPGAs boast hundreds of thousands of programmable ...
Design-Reuse

Tier Logic announces innovative 3D-FPGA technology: low-cost FPGAs & no-risk, timing-exact ASICs

Santa Clara, Calif., March 10, 2010. Tier Logic, Inc., a privately held fabless semiconductor company, today introduced its new 3D-based technology for FPGAs and ASICs, known respectively as its ...
Hackaday

Learning Verilog For FPGAs: Hardware At Last!

Getting into FPGA design isn’t a monolithic experience. You have to figure out a toolchain, learn how to think in hardware during the design, and translate that into working Verliog. The end goal is ...
Electronic Design

Cost-Conscious FPGAs Quadruple Logic Density

Nearly four times the logic density of previous low-cost FPGA families—that's the earmark of the just-released Cyclone FPGA family. With a logic architecture redesigned from the ground up, Altera now ...

QuickLogic Announces Orders for Strategic Radiation Hardened FPGA Development Kit

QuickLogic Corporation (NASDAQ: QUIK), a developer of embedded FPGA (eFPGA) Hard IP, Strategic Radiation Hardened, Antifuse and ruggedized FPGAs, announced today that it has received orders for its ...
EDN

FPGAs: System gates or logic cells/elements?

Arrgghhh! Will this never end? I just received an email from someone who asked: Hello Max, Would you please provide me any details about relation between Logic Elements (LEs) and System Gates count.
Hackaday

Who Could Possibly Need An FPGA With 9M Logic Cells And 35B Transistors?

Xilinx recently announced the Virtex UltraScale+ VU19P FPGA. Of course, FPGA companies announce new chips every day. The reason this one caught our attention is the size of it: nearly 9 million logic ...
Design-Reuse

FPGA based Complex System Designs: Methodology and Techniques

Today platform-FPGAs are fabricated in nanometer technologies with multi-million gate densities; hard/soft macros such as embedded processors, RAMs, multipliers, DSP blocks, analog cells and high ...
Electronics Weekly

TierLogic Reduces Cost Of FPGA, ASIC, & FPGA-ASIC Conversion

It’s good to see innovation taking place in programmables. This is a product area which has remained stuck in a $3 billion market niche for a decade. Silicon Valley start-up TierLogic today announces ...
Semiconductor Engineering

Logic Synthesis Basics For FPGA

In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all ...