Intel/Analog Devices' joint DSP design has crafted a new flexible ISA architecture. Analog Devices' (ADI's) BlackFin implementation delivers a 300-MHz, 16-bit DSP that supports dual MAC execution and ...
CEVA Announces Next Generation CEVA-TeakLite-III DSP Architecture Featuring Native 32-Bit Processing
CEVA-TeakLite-III extends the capabilities and more than doubles the performance of popular CEVA-TeakLite core targeting emerging consumer and wireless applications SAN JOSE, Calif. -- May 31, 2007-- ...
Groomed for tough automotive designs, the AS5243 10-bit, redundant magnetic rotary encoder chip integrates Hall elements, an analog front end, and digital signal processing into a thin QFN package.
Tensilica, Inc. has introduced the high-performance, small, low-power ConnX D2 16-bit dual-MAC (Multiply Accumulator) DSP (Digital Signal Processor) engine for its proven Xtensa LX dataplane processor ...
Fourth generation TeakLite® DSP architecture offered in a series of four DSP cores, differing in performance, die size and system interfaces; Incorporates smart power management technology and ...
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